Semiconductor device comprising extensions produced from material with a low melting point

ABSTRACT

A semiconductor device comprises a gate electrode ( 1 ) and a gate insulating layer ( 2 ) both surrounded by a spacer ( 3 ) and produced on a surface (S) of a substrate ( 100 ) of a first semiconductor material. The device also comprises a source region ( 4 ) and a drain region ( 5 ) both situated below the surface of the substrate, respectively on two opposite sides of the gate electrode ( 1 ). The source region and the drain region each comprise a portion of a second semiconductor material ( 6, 7 ) disposed on the substrate ( 100 ) and extending between the substrate ( 100 ) and the spacer ( 3 ). The second material has a melting point lower than the melting point of the first material. The portions of second material ( 6, 7 ) constitute extensions of the source ( 4 ) and drain ( 5 ) regions. The semiconductor device can be an MOS transistor.

The present invention relates to a semiconductor device produced on thesurface of a substrate, comprising extensions of a special type. Itapplies in particular to a field effect transistor, produced accordingto MOS (“Metal Oxide Semiconductor”) technology.

The extensions (“tip regions” in English), also known by the term LDD(“Low Doped Drain”), are parts of the source and drain regions of an MOStransistor, situated close to the respective ends of a channel disposedbetween the source and the drain. They extend to a shallow depth belowthe surface of the substrate which carries the transistor, as far asapproximately 50 nanometers. They are in general implanted during aspecific step, performed with a low-energy implantation beam. They havea conduction type identical to that of the source and drain regions,with concentrations of electrical carriers which are lower than those ofthe source and drain regions. The tip regions allow precise control ofthe electrical conduction of the source and drain regions at the ends ofthe channel. It is then possible to obtain a high level ofreproducibility of the operating characteristics of mass-produced MOStransistors.

It becomes more difficult to produce tip regions of an MOS transistor asthe dimensions of the transistor decrease, that is to say the level ofintegration on silicon increases. In particular, the doping elements ofthe parts of the source and drain have a tendency to diffuse in the tipregions when a carrier activation heating is carried out, even if thisheating is produced by means of a laser focused on the tip regions(“Laser Thermal Annealing” or LTA in English). The advantage afforded bythe tip regions then disappears.

The document U.S. Pat. No. 5,710,450 discloses a method of forming tipregions adapted for transistors of particularly small dimensions. Itdescribes several types of MOS transistor which comprise portions of asemiconductor material distinct from the material of the substrate andwhich are disposed on the substrate within the source and drain regions.These portions are used as sources of doping elements for the formationof the tip regions. These doping elements diffuse in the substrateduring a specific heating in order to confer the required electricalbehavior on the tip regions. The temperature during heating must bebetween 800° C. and 1000° C. in order to cause effective diffusion ofthese doping elements and thus confer on the tip regions the requiredconcentration of electrical carriers. However, this high temperaturecauses locally a melting of the materials at the interface between thesilicon substrate and insulating parts disposed around each transistor,known by the acronym STI (standing for “Shallow Trench Insulator”) inthe jargon of persons skilled in the art. It also causes a deformationof the gate electrode of the MOS transistors.

One aim of the present invention is to propose a semiconductor device ofa novel type, comprising tip regions compatible with a high level ofintegration, and which does not have the aforementioned drawbacks.

The invention relates to a semiconductor device comprising a gateelectrode and a gate insulating layer produced on part of the surface ofa substrate in a first semiconductor material. The gate electrode andthe gate insulating layer are surrounded, in a plane parallel to thesurface of the substrate, by an insulant known as a spacer. The gateinsulating layer is disposed between the substrate and the gateelectrode. The device also comprises a source region and a drain regionsituated below the surface of the substrate, at a level of two oppositesides of the gate electrode, respectively. The source region and thedrain region each contain electrical carriers of the same given type,with respect to first concentrations. They also each comprise a portionof a second semiconductor material disposed on the substrate below thelevel of the gate insulating layer in a direction perpendicular to thesurface of the substrate. Each portion of second material extends atleast partially between the substrate and the spacer, substantially asfar as a limit coming into line, in said perpendicular direction, withone of the opposite sides of the gate electrode. Said portions of secondmaterial are doped with doping elements in order to create electricalcarriers of said given type, with second concentrations less than saidfirst concentrations. The portions of second material have a meltingpoint lower than the melting point of said first material.

According to the invention, each portion of second semiconductormaterial at least partially fulfills a function of extension of thesemiconductor device. It can be selectively melted by heating to atemperature intermediate between the melting points of the substratesand extension. Such a heating activates the electrical carriers of thisportion without damaging the other elements of the device. It also makesit possible to distribute the doping elements in a substantially uniformfashion in each portion of second material.

When the heating is carried out by means of a laser, the portions ofsecond material advantageously have an ability to absorb a lightradiation greater than the absorption ability of the first material forthe same light radiation.

When the first material is based on silicon, the second material can bebased on germanium or based on an alloy of silicon and germanium (of theSixGe1−x type, where x is a number between 0 and 1). This is because themelting points of silicon and germanium are respectively 900° C. and500° C. approximately.

The invention also relates to a method of manufacturing a semiconductordevice of the above type.

The invention will be further described with reference to examples ofembodiments shown in the drawings to which, however, the invention isnot restricted.

FIG. 1 is a view in section of an MOS transistor produced according to afirst variant of the invention;

FIGS. 2 and 3 illustrate two steps of manufacturing an MOS transistoraccording to FIG. 1;

FIGS. 4-7 illustrate steps of manufacturing an MOS transistor accordingto a second variant of the invention.

In these figures, for reasons of clarity, the dimensions of the variouscircuit parts depicted are not in proportion with actual dimensions. Allthese figures are views in section of a semiconductor device comprisingvarious materials attached to a semiconductor substrate. The views insection are considered in planes perpendicular to an initial surface ofthe substrate. In the figures, identical references correspond toidentical elements. The substrate is placed in the bottom part of eachfigure and D designates a direction perpendicular to the initial surfaceof the substrate, oriented upwards in the figures. The terms “on”,“under”, “above”, “below”, “upper” and “lower” are used hereinafter withreference to the direction D.

An MOS transistor is produced on the surface of a substrate 100 whichmay, for example, be made from monocrystalline silicon. In accordancewith FIG. 1, it comprises a source region 4 and a drain region 5produced by doping in the substrate 10, on each side of a conductionchannel 10. The regions 4 and 5 have electrical conduction of the sametype, n or p, distinct from that of the channel 10. They contain forthis purpose electrical carriers with a concentration of approximately2.10¹⁸ carriers per cubic centimeter.

Above the channel 10, a gate insulating layer 2 is disposed on thesurface S of the substrate 100. A gate electrode 1 makes it possible tocontrol the channel 10 through the layer 2. The layer 2 is made fromsilica (SiO₂), tantalum oxide (Ta₂O₅) or hafnium oxide (HfO₂), forexample, and the electrode 1 is made from polysilicon for example. Aninsulating spacer 3, for example made from silicon nitride (Si₃N₄),surrounds the electrode 1 and the layer 2 parallel to the surface S.

The substrate 100 is covered, respectively above the regions 4 and 5,with two portions of a layer of germanium 6 and 7, themselves coveredrespectively with two portions of a layer of silicon 8 and 9. Theportions 6 and 7 are situated below the level of the surface S presentabove the channel 10. The material of the layers 8 and 9 is, forexample, conductive silicon. The portions 8 and 9 protect the portions 6and 7 against any oxidation liable to impair the electrical propertiesof the latter. The portions 6-8 are extended to a limit in line with theopposite sides C1 and C2 of the electrode 1, between the spacer 3 andthe substrate 100. Two supplementary portions 6bis and 8bis,respectively in the same materials as the portions 6 and 7 on the onehand and 8 and 9 on the other hand, can also be present above theelectrode 1. The portions 8, 8bis and 9 can help to form metallicsilicide parts for producing electrical contacts on respectively theregion 4, the electrode 1 and the region 5.

The portions 6 and 7 are doped so as to create, within these portions, nor p electrical carriers, of the same type as those in the regions 4 and5. The concentration of these electrical carriers in the portions 6 and7 is for example around 5.10¹⁷ carriers per cubic centimeter. Theportions 6 and 7 then constitute tip regions of the MOS transistor.

A method of manufacturing the above MOS transistor is now described. Theelementary steps of the process carried out according to methods knownto persons skilled in the art are not disclosed in detail. Onlyindications are given concerning the combination of these elementarysteps in a given chronological order of execution, which characterizesthe invention.

The silicon substrate 100 initially comprises a doping well, of the n orp type, depending on the type of transistor envisaged. In accordancewith FIG. 2, the layer 2 is formed on a part P1 of the surface S of thesubstrate 100. The electrode 1 is next formed above the layer 2, and thespacer 3 is disposed around the layer 2 and electrode 1, parallel to thesurface S, according to one of the methods normally used formanufacturing MOS transistors.

Two surface films of the material of the substrate 100 are then removed(FIG. 3) respectively in two lateral parts P2 and P3 of the surface ofthe substrate, situated on two opposite sides of the part P1. Each partP2 or P3 extends between the substrate 100 and the spacer 3,substantially as far as a limit coming in line, with the direction D,with one of the sides C1 or C2 of the electrode 2. The two films areremoved, for example, by selective dissolving of the material of thesubstrate 100 in a solution containing chemical reagents selected so asto form soluble compounds with the atoms of the substrate. When theelectrode 1 is in the same material as the substrate 100, an upper partP4 of the electrode 1 can be removed simultaneously.

The source 4 and drain 5 regions, situated below the surface S of thesubstrate 100, at a level of two lateral parts P2 and P3, respectively,are formed. The regions 4 and 5 are formed by ion implantation, in a waywhich is referred to as “autoaligned” with respect to the sides C1 andC2 of the spacer 3. Molecules of diborane B₂H₄ or phosphine PH₃ can beused for the implantation of the regions 4 and 5, in order to form a por n type MOS transistor, respectively. The regions 4 and 5 then eachcontain electrical carriers of the same given type, for example with theconcentration cited above in relation to FIG. 1.

Possibly the regions 4 and 5 may be implanted before the removal of thesurface films in the lateral parts P2 and P3.

On the substrate 100, in each lateral part P2 and P3, a portion 6 orrespectively 7 of a semiconductor extension material distinct from thematerial of the substrate 100 is formed. This extension materialpossesses a melting point lower than the melting point of the materialof the substrate 100. When the substrate 100 is made from silicon, theextension material is for example germanium. Each portion 6 or 7 isextended substantially as far as a location coming in line, in thedirection D1, with the side C1 or C2 of the electrode 1 corresponding tosaid lateral part. The portions 6 and 7 contain doping elements, such asatoms of boron or phosphorus, so as to create electrical carriers of thesame given type as the regions 4 and 5. The doping elements of theportions 6 and 7 can be present initially in the extension material whenit is formed, or be added subsequently during a step of implantation ofthe extension material.

The portions 6 and 7 are formed, for example, using a chemical vapordeposition (CVD) process, using organometallic precursors containingatoms of the extension material. A continuous layer of the extensionmaterial is then obtained, which covers the whole of the substrate 100,the spacer 3 and the electrode 1. By combining masking and etching,parts of this layer are removed so as to leave only the portions 6, 6bisand 7.

The portions 6 and 7 are next heated to a temperature intermediatebetween the respective melting points of the material of the substrate100 and the extension material. A laser beam can be used for thisheating, which makes it possible to heat regions of the transistorcomprising the portions 6 and 7 respectively. In this case, theextension material is advantageously chosen so that it has an ability toabsorb the laser beam greater than the ability of the material of thesubstrate 100 to absorb the laser beam. The portions 6 and 7 are thusmelted. Once cooled, they contain electrical carriers at a substantiallyuniform concentration, and less than the concentration of electricalcarriers in the regions 4 and 5. This heating of the portions 6 and 7may possibly serve simultaneously as a heating activation for theelectrical carriers in the regions 4 and 5.

Finally, the encapsulation portions 8 and 9 are deposited respectivelyon top of the portions 6 and 7. The material of the portions 8 and 9 isfor example silicon. A process similar to that of the formation of theportions 6 and 7 can be used, adapted to the encapsulation materialused. An encapsulation portion 8bis can possibly be formedsimultaneously above the portion 6bis.

According to a first variant of the manufacturing method (FIG. 1),corresponding to FIGS. 1 to 3, the portions 6 and 7 are formed so that afree interstice remains between the upper surface of each portion 6, 7and the lower surface of the spacer 3 on the same side of the electrode1. The encapsulation portions 8, 9 are then deposited so that eachencapsulation portion 8, 9 extends in the interstice between the spacer3 and the portion 6 or 7 above which it is deposited. It extendssubstantially as far as a limit situated in line, in the direction D,with the side C1 or C2 of the electrode 1 corresponding to theencapsulation portion in question.

FIGS. 4-6 correspond to a second variant of the invention. Starting fromthe configuration in FIG. 2, the spacer 3 is removed selectively, forexample by dissolving of the material of the spacer 3 in a solutioncomprising specially selected chemical reagents. The configuration ofthe transistor depicted in FIG. 4 is then obtained. After its removal,the function of the spacer 3 is to limit the implantation of the regions4 and 5 at a distance from each side of the layer 2.

A fine layer 30 of a protective material is then depositedisotropically, for example silicon nitride (Si₃N₄), on the substrate100, on the ends of the layer 2 and on the uncovered sides C1 and C2 andthe top face of the electrode 1. The layer 30 has a thickness of 10nanometers for example. In the remainder of the method of producing thetransistor, the layer 30 can effect a separation between electricalcontacts taken on the region 4 and on the electrode 1 and, in the sameway, between electrical contacts taken on the region 3 and on theelectrode 1. For this reason, and because it is situated in place of thespacer 3, the layer 30 is also called a spacer.

The layer 30 is next exposed, through its upper surface, to adirectional etching plasma whose direction of bombardment is parallel tothe direction D. The layer 9 is thus eliminated in its parts orientedperpendicular to the direction D. The configuration of the transistoraccording to FIG. 5 is thus obtained.

Surface films of the material of the substrate 10 are then removed inthe parts P2 and P3, in the same way as before. According to theconfiguration of the transistor depicted in FIG. 6, the thickness of thefilms removed, in the direction D, is greater than the thickness of thelayer 30, measured parallel to the surface S.

Portions of extension material 6 and 7, formed as described above, thencomprise, in addition to parts of layers parallel to the surface S,edges parallel to the direction D which cover the material of thesubstrate 100 under the layer 30.

The method of manufacturing the MOS transistor is then continued asdescribed above. A doping implantation of the portions 6 and 7 iscarried out if these do not intrinsically comprise sufficient quantitiesof electrical carriers. Then the portions 6 and 7 are heated to atemperature greater than the melting point of the extension material.Encapsulation portions 8 and 9 can then be disposed on the portions 6and 7.

According to an improvement of the first and second variants of theinvention described above, portions of a fine layer of a silicon andgermanium alloy is deposited in the lateral parts P2 and P3. Thisdeposition is made between the removal of the surface films of materialof the substrate 100 and the formation of the portions 6 and 7. Suchportions of an alloy having a chemical composition intermediate betweenthe respective compositions of the materials of the substrate 100 andthe portions 6 and 7 reduces the interface stresses between thesematerials. They in particular facilitate the growth of the extensionmaterial under conditions of heteroepitaxy.

The invention has been described in the context of the production of anMOS transistor. It can be applied likewise to any semiconductor devicecomprising a surface junction, referred to as USJ (standing for “UltraShallow Junction” in English), which requires the use of an extension.

No reference sign between parentheses in the present text should beinterpreted limitingly. The verb “comprise” and its conjugations mustalso be interpreted broadly, that is to say as not excluding thepresence not only of elements or steps other than those listed aftersaid verb but also a plurality of elements or steps already listed aftersaid verb and preceded by the word “a” or “an”.

1. A semiconductor device comprising: a gate electrode and a gateinsulating layer produced on a part of the surface of a substrate of afirst semiconductor material having a given melting point, andsurrounded by an insulating spacer in a plane parallel to the surface ofthe substrate, the gate insulating layer being disposed between thesubstrate and the gate electrode, and a source region and a drain regionsituated under the surface of the substrate at the level of two oppositesides of the gate electrode, respectively, each region containingelectrical carriers of the same given type, with respective firstconcentrations, and each region comprising a portion of a secondsemiconductor material disposed on the substrate below the level of thegate insulating layer in a direction perpendicular to the surface of thesubstrate, each portion of second material extending at least partiallybetween the substrate and the spacer, under at least a portion of thespacer and substantially as far as a limit coming in line, in saidperpendicular direction, with one side of the gate electrode, saidportions of second material being doped with doping elements in order tocreate electrical carriers of said given type with second concentrationsless than said first concentrations, and said portions of secondmaterial having a melting point lower than the melting point of thefirst material.
 2. A device as claimed in claim 1, in which saidportions of second material have an ability to absorb a light radiationgreater than the absorption ability of the first material for the samelight radiation.
 3. A device as claimed in claim 1, in which the firstmaterial is based on silicon and the second material is based ongermanium or based on an alloy of silicon and germanium.
 4. A device asclaimed in claim 1, also comprising two encapsulation portions of saidsecond material, disposed respectively over the portions of secondmaterial, on a side opposite to the substrate.
 5. A device as claimed inclaim 4, in which each encapsulation portion extends between the spacerand the portion of second material above which said encapsulationportion is disposed, substantially as far as a limit situated in line,in said direction perpendicular to the surface of the substrate, withthe side of the gate electrode corresponding to said secondencapsulation portion.
 6. A device as claimed in claim 1, characterizedin that said device is an MOS transistor.
 7. A method of manufacturing asemiconductor device, comprising the following steps: a) a gateinsulating layer is formed on a part of a surface of a substrate of afirst semiconductor material having a given melting point; b) a gateelectrode is formed on top of the gate insulating layer; c) aninsulating spacer is formed, disposed around the gate insulating layerand the gate electrode, parallel to the surface of the substrate; d) twosurface films of the first material are removed respectively in twolateral parts of the surface of the substrate situated on two oppositesides of the surface part of the substrate carrying the gate insulatinglayer and the gate electrode, each lateral part extending between thesubstrate and the spacer substantially as far as a limit coming in linewith one of the opposite sides of the gate electrode, in a directionperpendicular to the surface of the substrate; e) a source region and adrain region are formed, each region being situated below the surface ofthe substrate at a level of said two lateral parts of the surface of thesubstrate, respectively, each region containing electrical carriers ofthe same given type with respective first concentrations; f) there isformed on the substrate, in each lateral part, a portion of a secondsemiconductor material under at least a portion of the spacer andsubstantially as far as a limit coming in line, in said perpendiculardirection, with the opposite side of the gate electrode corresponding tosaid lateral part, said portions of second material containing dopingelements in order to create electrical carriers of the given type, andhaving a melting point lower than the melting point of the firstmaterial; g) the portions of second material are heated to a temperatureintermediate between the respective melting points of the first andsecond materials, so that the portions of second material containelectrical carriers with second concentrations lower than said firstconcentrations.
 8. A method as claimed in claim 7, according to which,during step g), said portions of second material are heated using alaser beam.
 9. A method as claimed in claim 7, according to which, afterstep f), encapsulation portions are deposited respectively on top ofsaid portions of second material, on a side opposite to the substrate.10. A method as claimed in claim 7, according to which step e) isperformed before step d).
 11. A method as claimed in claim 7, whereinsteps a) through g) are performed successively.